公开(公告)号：US09575885B2

公开(公告)日：2017-02-21

申请号：US13915257

申请日：2013-06-11

Applicant: Silicon Motion, Inc.

Inventor： Chia-Hsin Chen ,  Kuo-Liang Yeh ,  Ken-Fu Hsu

IPC: G06F12/02 ,  G06F12/14

CPC classification number: G06F12/0246 ,  G06F12/1408

Abstract: A data storage apparatus has a transmission interface, a nonvolatile memory and a controller. The controller records a non-completed flag. When the controller starts a card opening process, the nonvolatile memory is configured under card opening, and the non-completed flag is set non-completed status. When the controller receives a format command form the transmission interface, the nonvolatile memory is formatted and the non-completed flag is set as completed status. When the controller receives a write command, the write data are scrambled before being written to the nonvolatile memory. When in non-completed status, when the controller receives a read command from the transmission interface, no matter whether the data corresponding to the requested address are scrambled, the data are descrambled and descrambled are provided via the transmission interface.

Abstract translation: 数据存储装置具有传输接口，非易失性存储器和控制器。 控制器记录未完成的标志。 当控制器开始卡打开处理时，非卡性存储器被配置在卡打开状态，非完成标志被设置为非完成状态。 当控制器从传输接口接收格式命令时，非易失性存储器被格式化，未完成标志被设置为完成状态。 当控制器接收到写入命令时，写入数据在写入非易失性存储器之前被加扰。 当处于非完成状态时，当控制器从传输接口接收到读命令时，无论与所请求的地址相对应的数据是否被加密，都经过传输接口对数据进行解扰和解扰。

公开(公告)号：US09606911B2

公开(公告)日：2017-03-28

申请号：US13942380

申请日：2013-07-15

Applicant: SILICON MOTION, INC.

Inventor： Chi-Lung Wang ,  Chia-Hsin Chen ,  Chien-Cheng Lin

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F12/0246 ,  G06F12/10 ,  G06F2212/7201

Abstract: A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.