Memory controller and method for controlling output of debug messages

    公开(公告)号:US20240028508A1

    公开(公告)日:2024-01-25

    申请号:US18213899

    申请日:2023-06-26

    CPC classification number: G06F12/0246

    Abstract: A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

    Memory controller and method for controlling output of debug messages

    公开(公告)号:US12222856B2

    公开(公告)日:2025-02-11

    申请号:US18213899

    申请日:2023-06-26

    Abstract: A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

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