MECHANISM CAPABLE OF PERFORMING ON-CHIP TEST AND VERIFICATION

    公开(公告)号:US20240310436A1

    公开(公告)日:2024-09-19

    申请号:US18122747

    申请日:2023-03-17

    Inventor: Tse-Yen Liu

    CPC classification number: G01R31/3177 G01R31/31725

    Abstract: An electronic device includes a functional circuit, a test mode circuit, and a verification circuit. The verification circuit generates and outputs the test waveform signals into the test mode circuit based on a clock signal provided from the test mode circuit, receives test result waveform signals from the test mode circuit when at least one test operation corresponding to the test pattern signal is performed, and compares the test result waveform signals with target result waveform signals to generate and output a failure result signal into the test mode circuit; the failure result signal is used to indicate whether at least one test bit failure occurs.

    Mechanism capable of performing on-chip test and verification

    公开(公告)号:US12253564B2

    公开(公告)日:2025-03-18

    申请号:US18122747

    申请日:2023-03-17

    Inventor: Tse-Yen Liu

    Abstract: An electronic device includes a functional circuit, a test mode circuit, and a verification circuit. The verification circuit generates and outputs the test waveform signals into the test mode circuit based on a clock signal provided from the test mode circuit, receives test result waveform signals from the test mode circuit when at least one test operation corresponding to the test pattern signal is performed, and compares the test result waveform signals with target result waveform signals to generate and output a failure result signal into the test mode circuit; the failure result signal is used to indicate whether at least one test bit failure occurs.

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