BYPASS PATH LOSS REDUCTION
    1.
    发明申请
    BYPASS PATH LOSS REDUCTION 有权
    旁路路径减少

    公开(公告)号:US20150318889A1

    公开(公告)日:2015-11-05

    申请号:US14678390

    申请日:2015-04-03

    CPC classification number: H04B1/18 H04B1/44 H04B7/04

    Abstract: Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.

    Abstract translation: 本公开的方面涉及减少与旁路路径相关联的插入损耗。 在一个实施例中,装置包括具有至少两个投射的第一开关,具有至少两个投射的第二开关,第一开关和第二开关之间的旁路路径,以及至少一个电感器。 至少一个电感器被配置为补偿与旁路路径相关联的电容,以使旁路路径的插入损耗减小。

    Bypass path loss reduction
    2.
    发明授权

    公开(公告)号:US09847804B2

    公开(公告)日:2017-12-19

    申请号:US14678390

    申请日:2015-04-03

    CPC classification number: H04B1/18 H04B1/44 H04B7/04

    Abstract: Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.

    BYPASS PATH LOSS REDUCTION
    3.
    发明申请

    公开(公告)号:US20200099410A1

    公开(公告)日:2020-03-26

    申请号:US16559421

    申请日:2019-09-03

    Abstract: Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.

    Bypass path loss reduction
    4.
    发明授权

    公开(公告)号:US10447323B2

    公开(公告)日:2019-10-15

    申请号:US15809231

    申请日:2017-11-10

    Abstract: Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.

    BYPASS PATH LOSS REDUCTION
    5.
    发明申请

    公开(公告)号:US20180183477A1

    公开(公告)日:2018-06-28

    申请号:US15809231

    申请日:2017-11-10

    Abstract: Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.

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