Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline
    1.
    发明申请
    Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline 有权
    串行操作流水线,算术装置,算术逻辑电路及运行方式采用串行运行管线

    公开(公告)号:US20030200237A1

    公开(公告)日:2003-10-23

    申请号:US10404182

    申请日:2003-04-01

    Inventor: Junichi Naoi

    CPC classification number: G06F9/30036 G06F9/30014 G06F9/3893

    Abstract: A general-purpose serial operation pipeline realizes a complicated processing flow with an extemporaneous and explosive amount of operations with respect to various data sizes. A plurality of arithmetic-logic circuits (SALCs) that are controlled individually, and that can be operated together with another arithmetic-logic circuit (SALC) are connected in a cascade manner to form a serial operation pipeline. At least one of the plural SALCs includes a line for outputting data from an upstream SALC to a downstream SALC, a line for feeding back reverse data from the downstream SALC to the upstream SALC, and latch circuits for latching the data on the respective lines, thereby being capable of feeding back data from an arbitrary SALC to another SALC.

    Abstract translation: 通用串行操作流水线实现了对于各种数据大小的临时和爆炸量的操作的复杂的处理流程。 分别控制并且可以与另一个算术逻辑电路(SALC)一起操作的多个算术逻辑电路(SALC)以级联方式连接以形成串行操作流水线。 多个SALC中的至少一个包括用于从上游SALC向下游SALC输出数据的线,用于将反向数据从下游SALC反馈到上游SALC的线以及用于将数据锁存在各个线上的锁存电路, 从而能够将数据从任意SALC反馈到另一个SALC。

    Rendering processing method and device, semiconductor device, rendering process program and recording medium
    2.
    发明申请
    Rendering processing method and device, semiconductor device, rendering process program and recording medium 审中-公开
    渲染处理方法和装置,半导体装置,渲染处理程序和记录介质

    公开(公告)号:US20030059114A1

    公开(公告)日:2003-03-27

    申请号:US10256047

    申请日:2002-09-25

    Inventor: Junichi Naoi

    CPC classification number: G06T15/005

    Abstract: A rendering processing device includes a subpixel buffer having a rendering region which corresponds to a display region of a display, a color buffer that registers a color value of a pixel, and a Z buffer for registering a Z value of the pixel, and renders the pixel in the rendering region in accordance with the color value and Z value of the pixel to be displayed. When there is a new pixel to be rendered, it is verified whether an empty region for registering the color value and Z value of the new pixel exists in the buffers and, or not, and when no empty region exists, the color value and Z value of the new pixel and the registered color values and Z values are compared with each other, the most approximate color values or Z values are integrated together to produce an empty region.

    Abstract translation: 渲染处理装置包括具有对应于显示器的显示区域的渲染区域的子像素缓冲器,注册像素的颜色值的彩色缓冲器和用于记录像素的Z值的Z缓冲器,并且使得 根据要显示的像素的颜色值和Z值,渲染区域中的像素。 当存在要渲染的新像素时,验证用于登记颜色值的空白区域和新像素的Z值是否存在于缓冲器中,或者不存在,并且当没有空区域存在时,颜色值和Z 将新像素的值和注册的颜色值和Z值彼此进行比较,将最近的颜色值或Z值集成在一起以产生空白区域。

    Image processing method
    3.
    发明申请
    Image processing method 有权
    图像处理方法

    公开(公告)号:US20020190983A1

    公开(公告)日:2002-12-19

    申请号:US10165282

    申请日:2002-06-07

    Inventor: Junichi Naoi

    CPC classification number: G06T17/20 G06T11/40 G06T15/04

    Abstract: The size of polygons for composing an object in computer graphics is compared with a predetermined threshold value. Each polygon not exceeding the threshold value is directly converted into pixels. On the other hand, each polygon having a size which exceeds the threshold value is divided, and the resultant polygons are compared again. This ensures efficient processing of the polygons without causing an expansion of the circuit configuration or a significant increase in cost. The processing of the polygons will never be affected by the size of the polygons.

    Abstract translation: 将用于组合计算机图形中的对象的多边形的大小与预定阈值进行比较。 每个不超过阈值的多边形直接转换为像素。 另一方面,将具有超过阈值的尺寸的每个多边形分割,并且再次比较所得到的多边形。 这确保了多边形的有效处理,而不会导致电路配置的扩展或成本的显着增加。 多边形的处理决不会受到多边形的大小的影响。

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