公开(公告)号：US08830403B1

公开(公告)日：2014-09-09

申请号：US14197243

申请日：2014-03-05

Applicant: Sony Corporation

Inventor： Satoshi Kametani ,  Nobuyuki Asakura ,  Junya Kameyama

IPC: H04N11/20 ,  H04N9/64 ,  H04N5/50

CPC classification number: H04N7/0127 ,  H04N7/013

Abstract: An image processing device includes: a control section configured to allow, upon receipt of a moving image that includes, in time-series order, an original image and a duplicate image, a frame memory to hold a partial region in the original image and a remaining region in the duplicate image, in which the duplicate image is a duplicate of the original image, and the remaining region is a region excluding a region that agrees with the partial region; and an image processing section configured to read a piece of data that includes the partial region and the remaining region from the frame memory a plurality of times, and perform image processing by processing any of the read pieces of data as the original image and the remaining piece of data as the duplicate image.

Abstract translation: 一种图像处理装置，包括：控制部，被配置为在接收到以时间序列顺序包括原始图像和复制图像的运动图像时，允许存储原始图像中的部分区域的帧存储器，以及 复制图像中的剩余区域，其中重复图像是原始图像的副本，并且剩余区域是除了与部分区域一致的区域之外的区域; 以及图像处理部，其被配置为多次从所述帧存储器中读取包括所述部分区域和所述剩余区域的数据，并且通过处理所述读取的数据片段中的任何一个作为原始图像并执行图像处理，并且剩余部分 作为重复图像的数据。

公开(公告)号：US09069490B2

公开(公告)日：2015-06-30

申请号：US14153252

申请日：2014-01-13

Applicant: Sony Corporation

Inventor： Keiji Morikawa ,  Satoshi Kametani ,  Makoto Imai ,  Kazumasa Nishimoto

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/12

Abstract: A source device includes: a low-speed data supply section configured to supply, as low-speed data, data generated in synchronization with a low clock signal out of clock signals having different frequencies, the low clock signal having a frequency lower than a predetermined value; a high-speed data supply section configured to supply, as high-speed data, data generated in synchronization with a high clock signal out of the clock signals, the high clock signal having a frequency higher than that of the low clock signal; a dividing section configured to divide the low-speed data into a predetermined number of pieces of data in accordance with a ratio between the frequencies of the high and low clock signals; and a data transmitting section configured to store the high-speed data and the divided pieces of low-speed data in data having a predetermined data size, and to transmit the stored data.

Abstract translation: 源装置包括：低速数据供给部，被配置为将具有不同频率的时钟信号中的低时钟信号同步地产生的数据作为低速数据提供，低频时钟信号的频率低于预定的频率 值; 高速数据提供部，被配置为提供与时钟信号不同的高时钟信号产生的数据作为高速数据，高频时钟信号的频率高于低时钟信号的频率; 分配部分，被配置为根据高和低时钟信号的频率之间的比例将低速数据划分成预定数量的数据; 以及数据发送部，被配置为将高速数据和分割的低速数据片段存储在具有预定数据大小的数据中，并发送存储的数据。

公开(公告)号：US20140267924A1

公开(公告)日：2014-09-18

申请号：US14197243

申请日：2014-03-05

Applicant: Sony Corporation

Inventor： Satoshi Kametani ,  Nobuyuki Asakura ,  Junya Kameyama

IPC: H04N7/01

CPC classification number: H04N7/0127 ,  H04N7/013

Abstract: An image processing device includes: a control section configured to allow, upon receipt of a moving image that includes, in time-series order, an original image and a duplicate image, a frame memory to hold a partial region in the original image and a remaining region in the duplicate image, in which the duplicate image is a duplicate of the original image, and the remaining region is a region excluding a region that agrees with the partial region; and an image processing section configured to read a piece of data that includes the partial region and the remaining region from the frame memory a plurality of times, and perform image processing by processing any of the read pieces of data as the original image and the remaining piece of data as the duplicate image.

Abstract translation: 一种图像处理装置，包括：控制部，被配置为在接收到以时间序列顺序包括原始图像和复制图像的运动图像时，允许存储原始图像中的部分区域的帧存储器，以及 复制图像中的剩余区域，其中重复图像是原始图像的副本，并且剩余区域是除了与部分区域一致的区域之外的区域; 以及图像处理部，其被配置为多次从所述帧存储器中读取包括所述部分区域和所述剩余区域的数据，并且通过处理所述读取的数据片段中的任何一个作为原始图像并执行图像处理，并且剩余部分 作为重复图像的数据。

公开(公告)号：US20140205046A1

公开(公告)日：2014-07-24

申请号：US14153252

申请日：2014-01-13

Applicant: Sony Corporation

Inventor： Keiji Morikawa ,  Satoshi Kametani ,  Makoto Imai ,  Kazumasa Nishimoto

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/12

Abstract: A source device includes: a low-speed data supply section configured to supply, as low-speed data, data generated in synchronization with a low clock signal out of clock signals having different frequencies, the low clock signal having a frequency lower than a predetermined value; a high-speed data supply section configured to supply, as high-speed data, data generated in synchronization with a high clock signal out of the clock signals, the high clock signal having a frequency higher than that of the low clock signal; a dividing section configured to divide the low-speed data into a predetermined number of pieces of data in accordance with a ratio between the frequencies of the high and low clock signals; and a data transmitting section configured to store the high-speed data and the divided pieces of low-speed data in data having a predetermined data size, and to transmit the stored data.

Abstract translation: 源装置包括：低速数据供给部，被配置为将具有不同频率的时钟信号中的低时钟信号同步地产生的数据作为低速数据提供，低频时钟信号的频率低于预定的频率 值; 高速数据提供部，被配置为提供与时钟信号不同的高时钟信号产生的数据作为高速数据，高频时钟信号的频率高于低时钟信号的频率; 分配部分，被配置为根据高和低时钟信号的频率之间的比例将低速数据划分成预定数量的数据; 以及数据发送部，被配置为将高速数据和分割的低速数据片段存储在具有预定数据大小的数据中，并发送存储的数据。