公开(公告)号：US20190393232A1

公开(公告)日：2019-12-26

申请号：US16016375

申请日：2018-06-22

申请人： Sou-Chi CHANG ,  Uygar E. AVCI ,  Daniel H. MORRIS ,  Seiyon KIM ,  Ashish V. PENUMATCHA ,  Ian A. YOUNG

发明人： Sou-Chi CHANG ,  Uygar E. AVCI ,  Daniel H. MORRIS ,  Seiyon KIM ,  Ashish V. PENUMATCHA ,  Ian A. YOUNG

IPC分类号： H01L27/11507 ,  H01L49/02 ,  G11C11/22

摘要： Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.