公开(公告)号：US20060190908A1

公开(公告)日：2006-08-24

申请号：US11375891

申请日：2006-03-15

申请人： Stanislav Bajuk ,  Jack Smith ,  Sebastian Ventrone

发明人： Stanislav Bajuk ,  Jack Smith ,  Sebastian Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068

摘要： A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

摘要翻译： 一种存储和修改寄存器传输语言（RTL）的方法和系统，描述逻辑类型。 在声明信号互连时，基于信号互连的类型为信号互连定义了寄存器传输语言的语言扩展。语言扩展允许不同的信号互连类型，例如与现场可编程门阵列（例如， FPGA）和标准单元存储在相同的文件阵列层次结构中，这种存储有助于改变逻辑类型，从而最终导致集成电路（IC）更小（使用更多的标准单元）或更灵活（使用更多的FPGA 在物理设计周期内执行从一个RTL类型到另一个RTL类型的转换，其中在屏蔽最终芯片设计之前执行组件（信息）的布线，定时和布局。