Memory tester with enhanced post decode
    1.
    发明授权
    Memory tester with enhanced post decode 有权
    内存测试仪,具有增强的后解码功能

    公开(公告)号:US06687861B1

    公开(公告)日:2004-02-03

    申请号:US09702631

    申请日:2000-10-31

    IPC分类号: G11C2900

    CPC分类号: G11C29/56

    摘要: The data path into a post decode mechanism is altered to allow post decode to process data before or as that data is placed into a destination memory structure in interior test memory. Other data will continue to be first placed into a memory structure in interior test memory before being applied to the post decode mechanism. Extensive masking capability coupled with copies of error tables allow incremental post decode analysis for a new test, and avoids counting of errors in locations that are already known to have failed during previous tests. Both errors within words and bit errors can be accumulated. The post decode mechanism is often capable of producing multiple type of results from a single pass through the data, whether applied on the fly or from a structure in interior test memory. The post decode mechanism has counters that count down from pre-loaded values representing thresholds for deciding something about error activity. A counts of zero produces a terminal count flag. The values of the various terminal count flags are available at any time as data to be logged in interior test memory. Counters are often reloaded with an initial count at the conclusion of one test phase and in preparation for a subsequent phase. Some overhead may be saved and utility added by arranging for the counters to have respective initial value registers from which they may be reloaded upon receipt of a single command. The presence of the terminal count flag for a counter can inhibit the reload of the counter from its initial value register.

    摘要翻译: 改变后解码机制的数据路径被改变以允许后解码在数据被放置到内部测试存储器中的目的地存储器结构之前或之前处理数据。 在应用到后解码机制之前,其他数据将继续首先被放置在内部测试存储器中的存储器结构中。 广泛的屏蔽功能加上错误表的副本允许对新测试进行增量的后解码分析,并避免在先前测试中已知已知失败的位置中的错误计数。 字和位错误中的两个错误都可以被累积。 后解码机制通常能够从单次通过数据产生多种类型的结果,无论是在飞行中还是从内部测试存储器中的结构应用。 后解码机制具有从表示阈值的预加载值倒数的计数器,用于确定关于错误活动的某些事件。 零计数产生终端计数标志。 各种终端计数标志的值随时可用作内部测试存储器中要记录的数据。 计数器通常在一个测试阶段结束时重新加载初始计数,并为后续阶段做准备。 通过安排计数器具有各自的初始值寄存器,可以节省一些开销,并且通过接收单个命令可以重新加载它们。 计数器的终端计数标志的存在可以阻止计数器从其初始值寄存器的重新加载。