公开(公告)号：US07127695B2

公开(公告)日：2006-10-24

申请号：US10434964

申请日：2003-05-09

申请人： Steve C. Huang ,  Ihao Chen

发明人： Steve C. Huang ,  Ihao Chen

IPC分类号： G06F17/50

CPC分类号： G01R31/318591 ,  G06F17/5068

摘要： For use with a design database and a timing database, a computer implemented process for electronic design automation comprising: receiving a netlist that includes cells interconnected by circuit paths, wherein a plurality of the cells are scan cells connected in at least one scan chain; ordering the scan cells according to a prescribed scan cell ordering rule so as to produce a plurality of ordering relationships among scan cells; assigning respective weights from a first category of one or more weights to respective prescribed scan cell order relationships among scan cells of the netlist; assigning respective weights from a second category of one or more weights to prescribed circuit path relationships among cells of the netlist; and determining a physical placement of the cells of the netlist, including the scan cells, using a cost function that places the cells according to the assigned weights.

摘要翻译： 为了与设计数据库和定时数据库一起使用，用于电子设计自动化的计算机实现过程包括：接收包括通过电路路径互连的单元的网表，其中多个单元是连接在至少一个扫描链中的扫描单元; 根据规定的扫描单元排序规则排序扫描单元，以便产生扫描单元之间的多个排序关系; 将来自一个或多个权重的第一类别的各个权重分配给所述网表的扫描单元之间的相应规定的扫描单元顺序关系; 将来自一个或多个权重的第二类别的各个权重分配给所述网表的小区之间的规定电路路径关系; 以及使用根据所分配的权重放置所述单元的成本函数来确定所述网表的单元的物理放置，包括所述扫描单元。

公开(公告)号：US06973631B2

公开(公告)日：2005-12-06

申请号：US10435329

申请日：2003-05-09

申请人： Steve C. Huang ,  Ihao Chen

发明人： Steve C. Huang ,  Ihao Chen

IPC分类号： G01R31/3185 ,  G06F17/50

CPC分类号： G01R31/318364 ,  G01R31/318378 ,  G01R31/318541 ,  G01R31/318555

摘要： A computer implemented process of inserting enhanced scan bypass in relation to a bypassed block in an integrated circuit design comprising: receiving an HDL description of the circuit design; wherein the HDL description includes a port specification HDL instruction that specifies port properties of a bypassed block; wherein the HDL description includes an enhanced bypass HDL instruction that specifies how many scan cells to provide per port of the bypassed block in a scan bypass circuit that bypasses the bypassed block; wherein the bypass HDL instruction includes a user-selectable option of at least zero or one or two scan cells per port; in response to the specification HDL instruction and the enhanced bypass HDL instruction, automatically generating a netlist portion that includes scan a bypass circuit that bypasses the bypassed block and that includes the specified number of scan cells per port.

摘要翻译： 一种在集成电路设计中相对于旁路块插入增强扫描旁路的计算机实现过程，包括：接收电路设计的HDL描述; 其中所述HDL描述包括指定旁路块的端口属性的端口规范HDL指令; 其中所述HDL描述包括增强旁路HDL指令，其指定绕过旁路块的扫描旁路电路中提供每个端口的旁路块的多少个扫描单元; 其中所述旁路HDL指令包括每个端口至少为零个或一个或两个扫描单元的用户可选择选项; 响应于规范HDL指令和增强旁路HDL指令，自动生成包括扫描绕过旁路块的旁路电路并且包括每个端口的指定数量的扫描单元的网表部分。

公开(公告)号：USD324060S

公开(公告)日：1992-02-18

申请号：US362298

申请日：1989-06-06

申请人： Steve C. Huang

设计人： Steve C. Huang

公开(公告)号：US07134106B2

公开(公告)日：2006-11-07

申请号：US10821505

申请日：2004-04-09

申请人： Steve C. Huang ,  Yong Fan ,  Ihao Chen

发明人： Steve C. Huang ,  Yong Fan ,  Ihao Chen

IPC分类号： G06F11/00 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/14

摘要： Method and system for providing a computer implemented process of performing design for testability analysis and synthesis in an integrated circuit design includes partitioning each logic block in an integrated circuit design based on one or more boundaries of multi-cycle initial setup sequence, excluding one or more partitioned logic blocks with multi-cycle initial setup sequence from valid candidate blocks, selecting a constraint setting set, extracting a subset of constraint settings from the selected constraint setting set, applying the extracted subset of constraint settings to the integrated circuit design, performing design for testability analysis and synthesis on the valid candidate blocks, performing scan cell replacement. The scan cell replacement may include performing class selection from a cell library and a gate-level netlist based on affinity between cells, determining a target characterization, such as timing, power, area, for example, for the scan cell replacement, and replacing one or more cells with a corresponding one or more scan cells having the closest target characteristics.

摘要翻译： 用于提供在集成电路设计中执行用于可测试性分析和合成的设计的计算机实现过程的方法和系统包括基于多周期初始设置序列的一个或多个边界来划分集成电路设计中的每一个逻辑块，不包括一个或多个 分区逻辑块，具有来自有效候选块的多循环初始设置序列，选择约束设置集合，从所选择的约束设置集中提取约束设置的子集，将所提取的约束设置的子集应用于集成电路设计，执行设计 对有效候选块进行可测试性分析和综合，执行扫描单元更换。 扫描单元替换可以包括基于小区之间的亲和度从小区库和门级网表执行类选择，确定目标表征，例如定时，功率，区域，例如用于扫描小区替换，以及替换一个 或具有相应的一个或多个具有最接近的目标特征的扫描单元的单元。

公开(公告)号：US07080334B2

公开(公告)日：2006-07-18

申请号：US10435129

申请日：2003-05-09

申请人： Yong Fan ,  Steve C. Huang ,  Ihao Chen

发明人： Yong Fan ,  Steve C. Huang ,  Ihao Chen

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design, the method comprising: identifying a sequential element associated with a feedback loop in the design; producing a feedback loop signature associated with the feedback loop; wherein the signature includes an indication of feedback element instance type for each feedback element instance in the feedback loop, feedback position at each instance of a feedback element type in the feedback loop and a control signal for each instance of a feedback element type in the feedback loop; evaluating the feedback loop signature so as to generate associated stimulus logic; generating associated load logic; and inserting the generated stimulus logic to control a clock input to the sequential element; and inserting the generated load logic to provide a data input to the sequential element.

摘要翻译： 提供了一种用于在集成电路设计中导出门控时钟电路的计算机实现的方法，所述方法包括：识别与所述设计中的反馈回路相关联的顺序元件; 产生与反馈回路相关联的反馈循环签名; 其中所述签名包括所述反馈回路中的每个反馈元件实例的反馈元件实例类型的指示，所述反馈回路中的反馈元件类型的每个实例的反馈位置以及所述反馈中的反馈元件类型的每个实例的控制信号 循环; 评估反馈循环签名以产生相关联的刺激逻辑; 生成相关的负载逻辑; 以及插入所产生的刺激逻辑以控制对所述顺序元件的时钟输入; 并插入所产生的负载逻辑以向顺序元件提供数据输入。