-
公开(公告)号:US6051882A
公开(公告)日:2000-04-18
申请号:US905974
申请日:1997-08-05
申请人: Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Rin Lin
发明人: Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Rin Lin
IPC分类号: H01L21/768 , H01L23/522 , H01L23/52
CPC分类号: H01L23/5226 , H01L21/76807 , H01L21/76813 , H01L21/76877 , H01L21/76885 , H01L2924/0002
摘要: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.
摘要翻译: 一种制造导线的互连电平的方法,以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法,其使用反向镶嵌来形成导电线和通孔。 首先使用导电线图案来完全蚀刻该层以形成导电线开口。 开口完全被导电材料填充并平坦化,使得导电材料和绝缘层的表面是共面的。 通孔图案垂直于导电线对齐,并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。 由此在导电线的上部形成的开口用绝缘材料填充,以完成与绝缘层下部的导电线和层的上部向上突出的通孔的双镶嵌互连水平。 此外,通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。 所产生的互连级联结构包括具有向上和向下突出的通孔的导线。