REDUCING DATA READ LATENCY IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
    1.
    发明申请
    REDUCING DATA READ LATENCY IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
    在网络通信处理器架构中减少数据读取延迟

    公开(公告)号:US20110225588A1

    公开(公告)日:2011-09-15

    申请号:US12975823

    申请日:2010-12-22

    IPC分类号: G06F9/46

    摘要: Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

    摘要翻译: 描述的实施例为存储在网络处理器的至少一个共享存储器中的数据提供地址转换。 网络处理器的处理模块生成与多个接收到的分组中的每一个对应的任务。 分组分类器为每个任务生成上下文,每个上下文与指令线程相关联以应用于相应的分组。 指令的第一子集被存储在所述至少一个共享存储器内的树存储器中。 指令的第二子集存储在分组分类器的多线程引擎内的高速缓存中。 多线程引擎保持与高速缓存和树存储器中的第一和第二指令子集相对应的状态指示符,并且基于状态指示符,在处理线程以在指令数和物理地址之间转换时,访问查找表 在指令的第一和第二子集中的指令。

    Reducing data read latency in a network communications processor architecture
    2.
    发明授权
    Reducing data read latency in a network communications processor architecture 有权
    降低网络通信处理器架构中的数据读延迟

    公开(公告)号:US08505013B2

    公开(公告)日:2013-08-06

    申请号:US12975823

    申请日:2010-12-22

    IPC分类号: G06F9/46 G06F12/06

    摘要: Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

    摘要翻译: 描述的实施例为存储在网络处理器的至少一个共享存储器中的数据提供地址转换。 网络处理器的处理模块生成与多个接收到的分组中的每一个对应的任务。 分组分类器为每个任务生成上下文,每个上下文与指令线程相关联以应用于相应的分组。 指令的第一子集被存储在所述至少一个共享存储器内的树存储器中。 指令的第二子集存储在分组分类器的多线程引擎内的高速缓存中。 多线程引擎保持与高速缓存和树存储器中的第一和第二指令子集相对应的状态指示符,并且基于状态指示符,在处理线程以在指令数和物理地址之间转换时,访问查找表 在指令的第一和第二子集中的指令。

    Instruction breakpoints in a multi-core, multi-thread network communications processor architecture
    3.
    发明授权
    Instruction breakpoints in a multi-core, multi-thread network communications processor architecture 有权
    指令断点在多核,多线程网络通信处理器架构中

    公开(公告)号:US08868889B2

    公开(公告)日:2014-10-21

    申请号:US12976045

    申请日:2010-12-22

    摘要: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.

    摘要翻译: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器,用于从网络处理器的多个处理模块生成对应于由分组分类器接收到的任务的上下文的线程。 多线程指令引擎处理与从调度程序接收到的线程相对应的指令。 多线程指令引擎通过从分组分类器的指令存储器取出线程的指令来执行指令,并且确定是否使能网络处理器的断点模式。 如果断点模式被使能,并且获取的指令的断点指示器被设置,则分组分类器进入断点模式。 否则,如果未设置获取的指令的断点指示符,则多线程指令引擎执行读取的指令。

    INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
    4.
    发明申请
    INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
    多核心,多线程网络通信处理器架构中的指导性突破

    公开(公告)号:US20110225394A1

    公开(公告)日:2011-09-15

    申请号:US12976045

    申请日:2010-12-22

    IPC分类号: G06F9/312

    摘要: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.

    摘要翻译: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器,用于从网络处理器的多个处理模块生成对应于由分组分类器接收到的任务的上下文的线程。 多线程指令引擎处理与从调度程序接收到的线程相对应的指令。 多线程指令引擎通过从分组分类器的指令存储器取出线程的指令来执行指令,并且确定是否使能网络处理器的断点模式。 如果断点模式被使能,并且获取的指令的断点指示符被设置,则分组分类器进入断点模式。 否则,如果未设置获取的指令的断点指示符,则多线程指令引擎执行读取的指令。