公开(公告)号：US06383882B1

公开(公告)日：2002-05-07

申请号：US09860591

申请日：2001-05-21

申请人： Sun-wung Lee ,  Jae-phil Boo ,  Kyung-hyun Kim ,  Chang-ki Hong

发明人： Sun-wung Lee ,  Jae-phil Boo ,  Kyung-hyun Kim ,  Chang-ki Hong

IPC分类号： H01L21336

CPC分类号： H01L21/823468 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823443

摘要： A method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate polysilicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating layer and the gate polysilicon layer. Impurity ions are implanted and diffused using the gate spacer and the gate polysilicon layer as a mask layer to form a source/drain region in the substrate. An etching blocking layer is formed to cover the source/drain region, the gate spacer, and the gate polysilicon layer, and then, a dielectric layer to cover the etching blocking layer is formed. The dielectric layer is planarized, and the etching blocking layer on the gate polysilicon layer is exposed. The exposed etching blocking layer and a part of the gate spacer are etched, and a top surface and a top side of the gate polysilicon layer are exposed. A silicide layer is formed over the exposed part of the gate polysilicon layer.

摘要翻译： 一种使用选择性硅化物工艺制造MOS晶体管的方法，其中在硅衬底上依次形成栅极绝缘层和栅极多晶硅层，并且栅极间隔物形成在栅极绝缘层和栅极多晶硅层的侧壁上 。 使用栅极间隔物和栅极多晶硅层作为掩模层注入和扩散杂质离子，以在衬底中形成源极/漏极区域。 形成蚀刻阻挡层以覆盖源极/漏极区域，栅极间隔物和栅极多晶硅层，然后形成覆盖蚀刻阻挡层的电介质层。 介电层被平坦化，并且露出栅极多晶硅层上的蚀刻阻挡层。 蚀刻暴露的蚀刻阻挡层和栅极间隔物的一部分，并且露出栅极多晶硅层的顶表面和顶侧。 在栅极多晶硅层的暴露部分上形成硅化物层。