公开(公告)号：US08572532B1

公开(公告)日：2013-10-29

申请号：US13487157

申请日：2012-06-01

申请人： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky ,  Akash Khandelwal

发明人： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky ,  Akash Khandelwal

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock ports, creating launch and capture clocks, making exclusive clock groups of the launch clock and the capture clock for opposing clock ports to avoid the launch and capture clocks for each port affecting other internal data paths within the partition block, and associating common path pessimism removal information with a source latency of the capture clock to adjust timing at an end point of the internal data path.

摘要翻译： 公开了一种具有包括具有在块边界外部具有外部公共点的一对时钟路径的原始时钟信号的分区块的集成电路（IC）设计的定时分析的方法，包括：接收一个 分析IC设计，分析具有外部公共点的一对时钟路径，以确定分区块边界处的第一和第二时钟端口; 并为第一个和第二个时钟端口创建启动和捕获时钟，制作发射时钟的专用时钟组和相应时钟端口的捕获时钟，以避免每个端口的启动和捕获时钟影响分区块内的其他内部数据路径 并且将公共路径悲观消除信息与捕获时钟的源延迟相关联，以调整内部数据路径的终点处的定时。

公开(公告)号：US08977995B1

公开(公告)日：2015-03-10

申请号：US13586495

申请日：2012-08-15

申请人： Sumit Arora ,  Oleg Levitsky ,  Amit Kumar ,  Sushobhit Singh

发明人： Sumit Arora ,  Oleg Levitsky ,  Amit Kumar ,  Sushobhit Singh

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.

摘要翻译： 在一个实施例中，公开了一种设计集成电路的方法，包括接收多个顶层定时约束和对使用一个或多个嵌套分区具有多个层次的分区的层次结构的集成电路设计的描述; 响应于所述集成电路设计的描述，为所述多个分区的每个分区生成定时模型; 并且响应于对集成电路设计，定时模型和多个等级的描述，从每个级别的所有分区逐级生成定时预算，从分区的层次结构的最下一级开始到每个下一个较高级别 顶级时间约束。 请参阅分别披露和要求保护的其他实施例的详细描述和权利要求。