公开(公告)号：US20110156153A1

公开(公告)日：2011-06-30

申请号：US12905711

申请日：2010-10-15

申请人： Sven Beyer ,  Jande Hoentschel ,  Uwe Griebenow ,  Thilo Scheiper

发明人： Sven Beyer ,  Jande Hoentschel ,  Uwe Griebenow ,  Thilo Scheiper

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/7848

摘要： In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.

摘要翻译： 在用于在早期制造阶段形成高k金属栅电极结构的工艺策略中，可以使用预制半导体材料，以便减少半导体材料与栅电极结构的导电盖材料之间的肖特基势垒。 由于预制半导体材料的材料特性基本上均匀，可能会降低栅电极结构复杂构图工艺过程中任何与图案相关的不均匀性。 预制半导体材料可用于互补晶体管的栅电极结构。