公开(公告)号：US20210242205A1

公开(公告)日：2021-08-05

申请号：US17028459

申请日：2020-09-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Pochun WANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  G06F30/392 ,  G06F30/31

Abstract: A semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: relative to a first direction, first and second active regions arranged in a stack according to CFET-type configuration; first and second contact structures correspondingly electrically coupled to the first active region; third and fourth contact structures correspondingly electrically coupled to the second active region; a first layer of metallization over the stack which includes alpha logic conductors configured for logic signals (alpha logic conductors), and power grid (PG) conductors, the alpha logic and PG conductors being non-overlapping of each other; and a layer of metallization below the stack which includes beta logic conductors which are non-overlapping of each other; and wherein, relative to a second direction, each of the alpha logic, PG and beta logic conductors at least partially overlap one or more of the first, second, third and fourth contact structures.