公开(公告)号：US12048137B2

公开(公告)日：2024-07-23

申请号：US17404260

申请日：2021-08-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Po-Sheng Wang ,  Ru-Yu Wang ,  Yangsyu Lin ,  You-Cheng Xiao

IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

CPC分类号： H10B10/18 ,  H01L21/0259 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

摘要： A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.