公开(公告)号：US20090049325A1

公开(公告)日：2009-02-19

申请号：US12135189

申请日：2008-06-08

申请人： TAKANOBU NARUSE ,  Hirokatsu Noguchi ,  Kazuhide Kawade ,  Yoshiyuki Matsumoto

发明人： TAKANOBU NARUSE ,  Hirokatsu Noguchi ,  Kazuhide Kawade ,  Yoshiyuki Matsumoto

IPC分类号： G06F1/04

CPC分类号： G06F1/08 ,  G06F1/24

摘要： It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.

摘要翻译： 旨在提供一种能够从同步时钟的角度抑制突发电流变化的数据处理器。 数据处理器1包括时钟脉冲产生电路和对从时钟脉冲发生电路输出的输入时钟信号CLKi进行操作的电路模块。 在从上电复位期间或待机状态恢复的情况下，时钟脉冲发生电路逐步地将时钟信号的频率从低频变为高频。 这使得可以防止在从上电复位周期或待机状态恢复的情况下电源电流突然增加。