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公开(公告)号:US20240012299A1
公开(公告)日:2024-01-11
申请号:US17431155
申请日:2021-06-29
Inventor: Bangqing XIAO
IPC: G02F1/1345 , G09G3/36 , G02F1/1362
CPC classification number: G02F1/13454 , G09G3/3674 , G02F1/136286 , G02F1/136222 , G09G2300/0408
Abstract: The application discloses a display panel. The display panel includes: a dataline black matrix less (DBS) common electrode trace arranged in a routing area; a plurality of clock signal traces arranged in a first wiring area along a first direction; and a plurality of clock signal transfer lines connected to the plurality of clock signal traces in a one-to-one correspondence, wherein each of the clock signal transfer lines passes through the routing area and extends to a gate driver on array (GOA) unit area along the first direction, and at least one of the clock signal transfer lines is bent and arranged in the routing area.
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公开(公告)号:US20230102513A1
公开(公告)日:2023-03-30
申请号:US17279120
申请日:2021-03-08
Inventor: Bangqing XIAO
IPC: G02F1/1362 , H01L27/12 , G02F1/1343 , G02F1/1345 , G09G3/36
Abstract: Embodiments of the present invention disclose an array substrate and a display panel. The array substrate includes a first substrate, and a first metal layer, a second metal layer, and a first shielding line sequentially disposed on the first substrate. The first metal layer includes a plurality of scan lines, the second metal layer includes a signal transmission line electrically connected to all of the scan lines, and at least a part of an orthographic projection of a wiring part of the signal transmission line on the first substrate coincides with an orthographic projection of the first shielding line on the first substrate.
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