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公开(公告)号：US20210335302A1
公开(公告)日：2021-10-28
申请号：US16617306
申请日：2019-11-12
Inventor： Wenfang Li , Xianming Zhang
IPC: G09G3/36
Abstract: A gate driver on array (GOA) driving circuit including a power management IC and a level shifter circuit connected in order, wherein the level shifter circuit at least includes a first switch transistor, a second switch transistor, a detection unit, and a clock signal output terminal, the first switch transistor is connected to the second switch transistor, and the clock signal output terminal is configured to connect to the GOA circuit, and wherein the detection unit is connected to the first switch transistor and the second switch transistor respectively, configured to detect power consumption of the first switch transistor and the second switch transistor and feedback a detection result that is configured to control an on/off state of a signal output of the power management IC.
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公开(公告)号：US11223197B2
公开(公告)日：2022-01-11
申请号：US16621709
申请日：2019-07-04
Inventor： Yujia Liu , Xianming Zhang
IPC: H02M1/32 , H02H9/02 , G02F1/1362
Abstract: The present disclosure proposes an overcurrent protective circuit and a display panel. The overcurrent protective circuit includes a power supply circuit, a logic algorithm circuit, and an overcurrent protective circuit. The logic algorithm circuit is additionally arranged in the overcurrent protective circuit. The logic algorithm circuit set different threshold currents of overcurrent protection for the display panel according on different driving frequencies. The overcurrent protective circuit adjusts the protective components inside the overcurrent protective circuit in accordance with the set threshold currents. Therefore, the display panel is protected by the overcurrent protective circuit at different frequencies.
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公开(公告)号：US11158273B1
公开(公告)日：2021-10-26
申请号：US16617306
申请日：2019-11-12
Inventor： Wenfang Li , Xianming Zhang
IPC: G09G3/36
Abstract: A gate driver on array (GOA) driving circuit including a power management IC and a level shifter circuit connected in order, wherein the level shifter circuit at least includes a first switch transistor, a second switch transistor, a detection unit, and a clock signal output terminal, the first switch transistor is connected to the second switch transistor, and the clock signal output terminal is configured to connect to the GOA circuit, and wherein the detection unit is connected to the first switch transistor and the second switch transistor respectively, configured to detect power consumption of the first switch transistor and the second switch transistor and feedback a detection result that is configured to control an on/off state of a signal output of the power management IC.
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