公开(公告)号：US20210327325A1

公开(公告)日：2021-10-21

申请号：US16981730

申请日：2020-07-01

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Bangyin PENG ,  Ilgon KIM

IPC: G09G3/20

Abstract: A display panel and a test method thereof are provided in the preset disclosure. The display panel includes a first test area and a second test area; the display panel also includes an array substrate, a pixel electrode layer, and a light shielding layer, wherein the pixel electrode layer includes a plurality of pixel electrode units, and in a direction perpendicular to the array substrate, an orthographic projection of the light shielding layer covers orthographic projections of each main pixel electrode in the first test area and each sub-pixel electrode in the second test area.

公开(公告)号：US20230154427A1

公开(公告)日：2023-05-18

申请号：US16976775

申请日：2020-08-04

Applicant: TCL China Star Optoelectronics Technology Co., Ltd.

Inventor： Tianhong WANG ,  Yunxiao ZHONG ,  Ilgon KIM

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3688 ,  G09G2320/0233

Abstract: The present invention discloses an array substrate and a display device. The present invention employs a flip pixel framework of a DD+G wiring method, and a design of disposing a GOA circuit on a source electrode driver side. Because two of the data lines adjacently and parallelly enter an AA region, the gate electrode fanout wire and the two data lines are not adjacent to each other but parallelly extend in AA region, which prevents coupling between the gate electrode fanout wire and the data lines signal. The method of using the width of two pixel units to perform a layout of a GOA circuit of one level further facilitates achievement of the narrow border.

公开(公告)号：US20220013056A1

公开(公告)日：2022-01-13

申请号：US17053352

申请日：2020-08-04

Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Tianhong Wang ,  Yunxiao ZHONG ,  Ilgon KIM

IPC: G09G3/20

Abstract: The present application provides a display panel. The display panel includes multiple sub-pixels, multiple data lines, multiple scan lines, and multiple gate fan-out lines. Each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and any two adjacent gate fan-out lines are spaced by at least one sub-pixel group. A width of the gate fan-out line is not less than a sum of widths of the two data lines in the sub-pixel group.