公开(公告)号：US20250053519A1

公开(公告)日：2025-02-13

申请号：US18637758

申请日：2024-04-17

Applicant: Texas Instruments Incorporated

Inventor： David P. Foley ,  Venkatesh Natarajan

IPC: G06F12/14

Abstract: Systems and methods provide for inherited access permissions, thereby facilitating read and write access by called contexts. Hardware logic may enforce access permissions in the system. When a processor core executes code associated with a first context, the processor core generates a first hardware signal identifying the first context. The processor core may then switch from the first context to the second context due to the first context calling the second context. The processor core may then generate a second hardware signal identifying the calling (first) context, and then the first hardware signal identifies the called (second) context. The hardware logic that enforces the access permissions may then determine that the second context is being called and that the second context includes either direct access permissions or inherited access permissions associated with the calling (first) context.

公开(公告)号：US20250013747A1

公开(公告)日：2025-01-09

申请号：US18661021

申请日：2024-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthikeyan Rajamanickam ,  Venkatesh Natarajan ,  David P. Foley

IPC: G06F21/56

Abstract: Systems and methods may include bus monitoring hardware logic, where that bus monitoring hardware logic may monitor signals on one or more buses of processing unit, such as a central processing unit (CPU). Security logic may associate portions of code with code segregation units, such as links, stacks, and zones. Gating logic in the bus monitoring hardware logic may then enable or disable a monitoring function for a read or write access request based upon a link, stack, or zone identity associated with the piece of code making the read or write access request.

公开(公告)号：US12299451B2

公开(公告)日：2025-05-13

申请号：US17897016

申请日：2022-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David P. Foley ,  Alexander Tessarolo ,  Alan L. Davis

IPC: G06F9/38 ,  G06F9/30

Abstract: In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.

公开(公告)号：US20250053507A1

公开(公告)日：2025-02-13

申请号：US18429064

申请日：2024-01-31

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Rajasekhar Reddy Allu ,  David P. Foley ,  Amritpal S. Mundra

IPC: G06F12/02

Abstract: Methods, apparatus, systems, and articles of manufacture are described corresponding to immutable configuration of memory devices. An example memory includes a memory bank including a first portion and a second portion, the second portion configured to store configuration information that specifies whether the first portion is immutable; and a controller coupled to the memory bank, the controller configured to determine whether to prevent data from being written to the first portion based on the configuration information.