公开(公告)号：US20190326910A1

公开(公告)日：2019-10-24

申请号：US16378742

申请日：2019-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan BILHAN ,  Francisco A. CANO

IPC: H03K19/003 ,  H03K19/20 ,  H03K3/356

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

公开(公告)号：US20240037180A1

公开(公告)日：2024-02-01

申请号：US18071302

申请日：2022-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Donald E. STEISS ,  Timothy ANDERSON ,  Francisco A. CANO ,  Anthony Martin HILL ,  Kevin P. LAVERY ,  Arthur REDFERN

IPC: G06F17/16 ,  G06F7/523

CPC classification number: G06F17/16 ,  G06F7/523

Abstract: In examples, a device comprises control logic configured to detect an idle cycle, an operand generator configured to provide a synthetic operand responsive to the detection of the idle cycle, and a computational circuit. The computational circuit is configured to, during the idle cycle, perform a first computation on the synthetic operand. The computational circuit is configured to, during an active cycle, perform a second computation on an architectural operand.

公开(公告)号：US20190326909A1

公开(公告)日：2019-10-24

申请号：US16262327

申请日：2019-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan BILHAN ,  Francisco A. CANO

IPC: H03K19/003 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.