Smart Scan Options to Improve Wafer Die Yield

    公开(公告)号:US20240143890A1

    公开(公告)日:2024-05-02

    申请号:US18050151

    申请日:2022-10-27

    CPC classification number: G06F30/394 G06F30/347

    Abstract: A circuit includes: channel signal chains; configuration registers including a configuration register for each of the channel signal chains; channel data registers including a channel data register for each of the channel signal chains; a first communication interface coupled to the configuration registers via a daisy-chain connection; a second communication interface coupled to the set of channel data registers via respective parallel connections; and routing interfaces including a routing interface for each of the channel signal chains, each of the routing interfaces having a routing data input, a daisy-chain connection input, a parallel connection input, first and second control inputs, and a routing data output.

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