LOW LATENCY SERIAL BUS
    1.
    发明公开

    公开(公告)号:US20240356774A1

    公开(公告)日:2024-10-24

    申请号:US18240827

    申请日:2023-08-31

    Abstract: A serial bus control circuit includes a link layer control circuit. The link layer control circuit is configured to control isochronous data transfer over a serial bus. The link layer control circuit includes an isochronous cycle timer configured to provide a cycle frame that is less than 125 microseconds in duration. The link layer control circuit can be configured to set the isochronous cycle timer to provide a cycle frame duration that produces an isochronous transfer latency of no more than 50 microseconds.

Patent Agency Ranking