公开(公告)号：US11132203B2

公开(公告)日：2021-09-28

申请号：US14459416

申请日：2014-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/38

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

公开(公告)号：US20230273797A1

公开(公告)日：2023-08-31

申请号：US18314264

申请日：2023-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Shrey Sudhir Bhatia ,  Jeroen Vliegen

IPC: G06F9/38

CPC classification number: G06F9/3873 ,  G06F9/3838

Abstract: A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages.

公开(公告)号：US11868780B2

公开(公告)日：2024-01-09

申请号：US17412491

申请日：2021-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/22 ,  G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3877

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

公开(公告)号：US20210382721A1

公开(公告)日：2021-12-09

申请号：US17412491

申请日：2021-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/38

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.