公开(公告)号：US20210289233A1

公开(公告)日：2021-09-16

申请号：US17331159

申请日：2021-05-26

Applicant: Texas Instruments Incorporated

Inventor： Soyeb Nagori ,  Shyam Jagannathan ,  Deepak Kumar Poddar ,  Arun Shankar Kudana ,  Pramod Swami ,  Manoj Koul

IPC: H04N19/86 ,  H04N19/176 ,  H04N19/117 ,  H04N19/139 ,  H04N19/82

Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality of current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.

公开(公告)号：US20250045572A1

公开(公告)日：2025-02-06

申请号：US18408351

申请日：2024-01-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Varun Tripathi ,  Manu Mathew ,  Pramod Swami ,  Kumar Desappan

IPC: G06N3/0495

Abstract: Disclosed herein are systems and methods for performing post training quantization. A processor obtains fixed-point output values from a layer of an artificial neural network (ANN) wherein the layer includes fixed-point weights determined based on floating-point weights and a weight scaling factor determined based on an output scaling factor. Next, the processor converts the fixed-point output values to floating-point output values based on the output scaling factor. Then, the processor expands a range of floating-point values. Next, the processor calculates a new output scaling factor based on the expanded range of floating-point output values. Finally, the processor stores the new output scaling factor in an associated memory.

公开(公告)号：US20230252328A1

公开(公告)日：2023-08-10

申请号：US18153764

申请日：2023-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pramod Swami ,  Eppa Praveen Reddy ,  Jesse Villarreal ,  Kumar Desappan

IPC: G06N5/048 ,  G06F9/48

CPC classification number: G06N5/048 ,  G06F9/4818

Abstract: Disclosed herein are systems and methods for inference model scheduling of a multi priority inference model system. A processor determines an interrupt flag has been set indicative of a request to interrupt execution of a first inference model in favor of a second inference model. In response to determining that the interrupt flag has been set, the processor determines a state of the execution of the first inference model based on one or more factors. In response to determining the state of the execution is at a preemptable boundary, the processor deactivates the first inference model and activates the second inference model.

公开(公告)号：US11051046B2

公开(公告)日：2021-06-29

申请号：US16988978

申请日：2020-08-10

Applicant: Texas Instruments Incorporated

Inventor： Soyeb Nagori ,  Shyam Jagannathan ,  Deepak Kumar Poddar ,  Arun Shankar Kudana ,  Pramod Swami ,  Manoj Koul

IPC: H04N19/86 ,  H04N19/176 ,  H04N19/117 ,  H04N19/139 ,  H04N19/82

Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality of current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.

公开(公告)号：US09811607B2

公开(公告)日：2017-11-07

申请号：US14632822

申请日：2015-02-26

Applicant: Texas Instruments Incorporated

Inventor： Victor Cheng ,  Pramod Swami ,  Prashanth Viswanath

IPC: G06F17/30

CPC classification number: G06F17/30988

Abstract: A device includes an input array register, a determining component and a computing component. The input array register stores a sorted list of n elements as an input array having size n, n being an integer greater than or equal to two. The determining component creates a list of m elements as a mask array having a size m, m being an integer greater than or equal to one, one of the m elements being based on two adjacent of the n elements of the input array. The computing component performs a mathematical operation between the input array and the mask array to generate a list of p elements as an output array having a size p, p being an integer greater than or equal to 0, the p elements identifying unique elements within the n elements.

公开(公告)号：US20240338253A1

公开(公告)日：2024-10-10

申请号：US18361401

申请日：2023-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pramod Swami ,  Mihir Mody ,  Deepak Poddar

IPC: G06F9/50

CPC classification number: G06F9/5038

Abstract: Various examples disclosed herein relate to digital signal processing, and more particularly, to processing stages of multi-channel processing pipelines in batches according to an order. A method of such processing is provided and includes retrieving multi-channel data from a memory and processing the multi-channel data with a hardware accelerator implementing a multi-stage processing pipeline for each channel of a plurality of channels. The multi-stage processing pipelines can be arranged in a cyclically descending order based on a total number of stages of each multi-stage processing pipeline. Processing the multi-channel data includes sequentially processing a plurality of batches each including one or more stages from different multi-stage processing pipelines adjacent to each other in the cyclically descending order. Processing the plurality of batches may include processing corresponding ones of the stages in parallel.

公开(公告)号：US11831927B2

公开(公告)日：2023-11-28

申请号：US17331159

申请日：2021-05-26

Applicant: Texas Instruments Incorporated

Inventor： Soyeb Nagori ,  Shyam Jagannathan ,  Deepak Kumar Poddar ,  Arun Shankar Kudana ,  Pramod Swami ,  Manoj Koul

IPC: H04N19/86 ,  H04N19/176 ,  H04N19/117 ,  H04N19/139 ,  H04N19/82

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/139 ,  H04N19/176 ,  H04N19/82

Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality of current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.

公开(公告)号：US20150023436A1

公开(公告)日：2015-01-22

申请号：US14337669

申请日：2014-07-22

Applicant: Texas Instruments Incorporated

Inventor： Soyeb Nagori ,  Shyam Jagannathan ,  Deepak Kumar Poddar ,  Arun Shankar Kudana ,  Pramod Swami ,  Manoj Koul

IPC: H04N19/86 ,  H04N19/583

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/139 ,  H04N19/176 ,  H04N19/82

Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.

Abstract translation: 本公开提供了一种噪声滤波器。 噪声滤波器包括运动估计（ME）引擎。 ME接收当前帧和参考帧。 包括当前块和参考帧的当前帧包括多个参考块。 ME引擎生成最终的运动矢量。 当前块包括多个当前像素。 运动补偿单元基于最终运动矢量和参考帧产生运动补偿块。 运动补偿块包括多个运动补偿像素。 加权平均滤波器分别乘以第一权重和第二权重的多个当前像素中的每个当前像素和多个运动补偿像素的对应运动补偿像素。 加权平均滤波器生成滤波块。 块去除单元耦合到加权平均滤波器并去除滤波块中的伪像。

公开(公告)号：US20240202500A1

公开(公告)日：2024-06-20

申请号：US18067089

申请日：2022-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Varun Tripathi ,  William Leven ,  Pramod Swami

IPC: G06N3/0464

CPC classification number: G06N3/0464

Abstract: Disclosed herein are improved systems and methods for accelerated 2D dilated convolution. A processor determines an offset based on a dilation factor of the 2D dilated convolution. The processor selects rows of data from the 2D input in phases based on the offset and loads an input feature panel without overwriting data that has not yet been consumed by the 2D dilated convolution processor. As the 2D dilated convolution processor performs the convolution iterations, the processor continues to load additional data for the convolution. As the convolution iterations are completed, the processor spaces result of the 2D dilated convolution into a matrix such that results of each phase are spaced based on the offset.

公开(公告)号：US20240046413A1

公开(公告)日：2024-02-08

申请号：US18175185

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pramod Swami ,  Anshu Jain ,  Eppa Praveen Reddy ,  Kumar Desappan ,  Soyeb Nagori ,  Arthur Redfern

IPC: G06T3/40

CPC classification number: G06T3/4046

Abstract: Technology is disclosed herein to execute an inference model by a processor which includes a reshape layer. In an implementation, the reshape layer of the inference model receives an output produced by a previous layer of the inference model and inserts padding into the output, then supplies the padded output as an input to a next layer of the inference model. In an implementation, the inference model includes a stitching layer at the beginning of the inference model and an un-stitch layer at the end of the model. The stitching layer of the inference model stitches together multiple input images into an image batch and supplies the image batch as an input to a subsequent layer. The un-stitch layer receives output from a penultimate layer of the inference model and unstitches the output to produce multiple output images corresponding to the multiple input images.