公开(公告)号：US20140129908A1

公开(公告)日：2014-05-08

申请号：US13669447

申请日：2012-11-06

Applicant: TEXAS INSTRUMENTS, INCORPORATED

Inventor： Prohor Chowdhury ,  Alexander Tessarolo

IPC: H03M13/23

CPC classification number: H03M13/4107

Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.

Abstract translation: 适用于维特比解码的解码系统包括包括状态度量阵列，蝶形单元和约束长度多路复用器的解码器。 状态度量阵列包括寄存器，其中每个寄存器被布置成存储用于处理的状态度量。 蝶形单元包括一组蝴蝶元件，其中每个蝶形元件被布置成与蝴蝶单元中的其它蝶形元件并行生成中间状态度量。 约束长度多路复用器单元被布置为响应于中间状态度量和存储在约束长度寄存器中的维特比约束长度值来生成新的状态度量。 也可以响应于约束长度来生成转换位。

公开(公告)号：US08943392B2

公开(公告)日：2015-01-27

申请号：US13669447

申请日：2012-11-06

Applicant: Texas Instruments, Incorporated

Inventor： Prohor Chowdhury ,  Alexander Tessarolo

IPC: H03M13/03

CPC classification number: H03M13/4107

Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.

Abstract translation: 适用于维特比解码的解码系统包括包括状态度量阵列，蝶形单元和约束长度多路复用器的解码器。 状态度量阵列包括寄存器，其中每个寄存器被布置成存储用于处理的状态度量。 蝶形单元包括一组蝴蝶元件，其中每个蝶形元件被布置成与蝴蝶单元中的其它蝶形元件并行生成中间状态度量。 约束长度多路复用器单元被布置为响应于中间状态度量和存储在约束长度寄存器中的维特比约束长度值来生成新的状态度量。 也可以响应于约束长度来生成转换位。

公开(公告)号：US09311274B2

公开(公告)日：2016-04-12

申请号：US14056111

申请日：2013-10-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prohor Chowdhury ,  Alexander Tessarolo

IPC: G06F15/00 ,  G06F17/14

CPC classification number: G06F17/142

Abstract: A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2N)×(10×log2N) times.

Abstract translation: 系统包括存储体和控制单元。 控制单元被配置为通过对N个输入项执行FFT计算，并且通过对（1/2×log2N）×（10×log2N）倍的存储体进行基于合并的二进制蝶形运算进行FFT计算。