公开(公告)号：US20230343375A1

公开(公告)日：2023-10-26

申请号：US18203806

申请日：2023-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Divya Kaur ,  Rishav Gupta

IPC: G11C7/10 ,  H03K19/007

CPC classification number: G11C7/1084 ,  H03K19/007

Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

公开(公告)号：US11705169B2

公开(公告)日：2023-07-18

申请号：US17537872

申请日：2021-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Divya Kaur ,  Rishav Gupta

IPC: G11C7/10 ,  H03K19/007

CPC classification number: G11C7/1084 ,  H03K19/007

Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

公开(公告)号：US12131799B2

公开(公告)日：2024-10-29

申请号：US18203806

申请日：2023-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Divya Kaur ,  Rishav Gupta

IPC: G11C7/10 ,  H03K19/007

CPC classification number: G11C7/1084 ,  H03K19/007

Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

公开(公告)号：US20220238143A1

公开(公告)日：2022-07-28

申请号：US17537872

申请日：2021-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Chauhan ,  Divya Kaur ,  Rishav Gupta

IPC: G11C7/10 ,  H03K19/007

Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.