公开(公告)号：US11139916B2

公开(公告)日：2021-10-05

申请号：US16936065

申请日：2020-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay Pennam ,  Vamsi Krishna Kandalla ,  Brahmendra Reddy Yatham ,  Shailesh Wardhen ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu

IPC: H04L1/00 ,  H04B1/04

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

公开(公告)号：US11689316B2

公开(公告)日：2023-06-27

申请号：US17462055

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay Pennam ,  Vamsi Krishna Kandalla ,  Brahmendra Reddy Yatham ,  Shailesh Wardhen ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu

IPC: H04L1/00 ,  H04B1/04

CPC classification number: H04L1/0044 ,  H04B1/04 ,  H04L1/0042 ,  H04L1/0047 ,  H04L1/0061

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.