公开(公告)号：US20250117326A1

公开(公告)日：2025-04-10

申请号：US18987237

申请日：2024-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F12/02

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed data segments into faster access memory. The technique creates shadow copies of the most frequently accessed data segments in the faster access memory, which is associated with lower latency. Access frequencies of the data segments for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.

公开(公告)号：US20230342292A1

公开(公告)日：2023-10-26

申请号：US17729252

申请日：2022-04-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a centralized transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in memory devices associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use, and the technique flexible for different memory hierarchies.

公开(公告)号：US20240248839A1

公开(公告)日：2024-07-25

申请号：US18426053

申请日：2024-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in the faster access memory, which is associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.