Rdson-based current sensing system

    公开(公告)号:US11949320B2

    公开(公告)日:2024-04-02

    申请号:US17678220

    申请日:2022-02-23

    CPC classification number: H02M1/0009 H02M3/158

    Abstract: A device includes a current mirror, a switch, first and second current paths, first and second buffers, a variable resistor, a temperature-sensing circuit, and a controller. The first current path is coupled between the current mirror's input and the switch. The switch switches between ground and a transistor based on a control signal. The second current path is coupled between a first current mirror output and ground. The first buffer is coupled to a second current mirror output. The second buffer is coupled to the variable resistor, which is coupled to the first buffer. The temperature-sensing circuit provides a device temperature to the controller, which is coupled to a first buffer output and determines a first adjustment to the first and second current paths and a second adjustment to the variable resistor based on the device temperature.

    Comparator architecture for reduced delay and lower static current

    公开(公告)号:US11595033B2

    公开(公告)日:2023-02-28

    申请号:US17515018

    申请日:2021-10-29

    Abstract: Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.

    COMPARATOR ARCHITECTURE FOR REDUCED DELAY AND LOWER STATIC CURRENT

    公开(公告)号:US20220166419A1

    公开(公告)日:2022-05-26

    申请号:US17515018

    申请日:2021-10-29

    Abstract: Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.

Patent Agency Ranking