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1.发明授权公开(公告)号：US11257076B2
公开(公告)日：2022-02-22
申请号：US16093162
申请日：2017-03-27
发明人： Glenn Gulak , Alhassan Khedr
IPC分类号： G06Q20/38 , H04L9/00 , G16H10/40 , G16H10/60 , G06N20/00 , A61B5/00 , H04L9/30 , H04L29/06 , G06Q20/08
摘要： Systems, methods and devices for validating and performing operations on homomorphically encrypted data are described herein. The methods include securely transmitting and extracting information from encrypted data without fully decrypting the data. A data request may include an encrypted portion including a set of confidential data. One or more sets of encrypted comparison data may be then retrieved from a database in response to the data request. The encrypted set of confidential data from the data request is then compared with each set of encrypted comparison data using one or more homomorphic operations to determine which set of encrypted comparison data matches the encrypted set of confidential data. If there is a match, this validates the set of confidential data. An encrypted indicator is then generated indicating success or failure in validating the set of confidential data, which may then be forwarded to a party associated with the data request.
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公开(公告)号：US20210028921A1
公开(公告)日：2021-01-28
申请号：US16921028
申请日：2020-07-06
发明人： Alhassan Khedr , Glenn Gulak
摘要： Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.
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3.发明申请公开(公告)号：US20190222412A1
公开(公告)日：2019-07-18
申请号：US16365450
申请日：2019-03-26
发明人： Alhassan Khedr , Glenn Gulak
CPC分类号： H04L9/008 , G06F7/50 , G06F9/3001 , G06F9/30029 , G06F2207/4802 , G09C1/00 , H04L9/0618 , H04L2209/12
摘要： Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, a first multiplier, and first selection circuitry coupled to the first adder/subtractor and the first multiplier. Respective bypass paths selectively bypass the first adder/subtractor and the first multiplier. The low input word path includes a second adder/subtractor, a second multiplier, and second selection circuitry coupled to the second adder/subtractor and the second multiplier. Respective bypass paths selectively bypass the second adder/subtractor and the second multiplier. The first and second selection circuitry is responsive to different mode control signals to reconfigure the low and high input word paths into different logic processing units.
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4.发明申请公开(公告)号：US20180294950A1
公开(公告)日：2018-10-11
申请号：US15674864
申请日：2017-08-11
发明人： Alhassan Khedr , Glenn Gulak
CPC分类号： H04L9/008 , G06F7/50 , G06F9/3001 , G06F9/30029 , G06F2207/4802 , G09C1/00 , H04L9/0618 , H04L2209/12
摘要： Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) homomorphic processor chip is disclosed. The IC homomorphic processor chip includes at least one processor slice. Each processor slice includes local control circuitry, a numeric theoretic transform (NTT) butterfly unit, and on-chip memory. The NTT butterfly unit is responsive to the local control circuitry to operate in multiple modes for performing operations on encrypted data using homomorphic encryption. Each mode is associated with a different configuration of the NTT butterfly unit.
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公开(公告)号：US11456856B2
公开(公告)日：2022-09-27
申请号：US16921028
申请日：2020-07-06
发明人： Alhassan Khedr , Glenn Gulak
摘要： Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.
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6.发明申请公开(公告)号：US20190268135A1
公开(公告)日：2019-08-29
申请号：US16365463
申请日：2019-03-26
发明人： Alhassan Khedr , Glenn Gulak
摘要： Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.
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7.发明申请公开(公告)号：US20190182216A1
公开(公告)日：2019-06-13
申请号：US16093162
申请日：2017-03-27
发明人： Glenn Gulak , Alhassan Khedr
摘要： Systems, methods and devices for validating and performing operations on homomorphically encrypted data are described herein. The methods include securely transmitting and extracting information from encrypted data without fully decrypting the data. A data request may include an encrypted portion including a set of confidential data. One or more sets of encrypted comparison data may be then retrieved from a database in response to the data request. The encrypted set of confidential data from the data request is then compared with each set of encrypted comparison data using one or more homomorphic operations to determine which set of encrypted comparison data matches the encrypted set of confidential data. If there is a match, this validates the set of confidential data. An encrypted indicator is then generated indicating success or failure in validating the set of confidential data, which may then be forwarded to a party associated with the data request.
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8.发明授权公开(公告)号：US10298385B2
公开(公告)日：2019-05-21
申请号：US15674864
申请日：2017-08-11
发明人： Alhassan Khedr , Glenn Gulak
摘要： Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) homomorphic processor chip is disclosed. The IC homomorphic processor chip includes at least one processor slice. Each processor slice includes local control circuitry, a numeric theoretic transform (NTT) butterfly unit, and on-chip memory. The NTT butterfly unit is responsive to the local control circuitry to operate in multiple modes for performing operations on encrypted data using homomorphic encryption. Each mode is associated with a different configuration of the NTT butterfly unit.
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公开(公告)号：US11870881B2
公开(公告)日：2024-01-09
申请号：US17953224
申请日：2022-09-26
发明人： Alhassan Khedr , Glenn Gulak
CPC分类号： H04L9/008 , G09C1/00 , H04L9/0618 , G06F7/50 , G06F9/3001 , G06F9/30029 , G06F2207/4802 , H04L2209/12
摘要： Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.
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公开(公告)号：US20230086526A1
公开(公告)日：2023-03-23
申请号：US17953224
申请日：2022-09-26
发明人： Alhassan Khedr , Glenn Gulak
摘要： Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.
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