公开(公告)号：US20220020642A1

公开(公告)日：2022-01-20

申请号：US17487987

申请日：2021-09-28

Applicant: TOKYO ELECTRON LIMITED

Inventor： Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  David O'meara ,  Jeffrey Smith

IPC: H01L21/768 ,  H01L21/02

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.