公开(公告)号：US20210272898A1

公开(公告)日：2021-09-02

申请号：US17324897

申请日：2021-05-19

Applicant: TOPPAN PRINTING CO.,LTD.

Inventor： Fusao TAKAGI

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/50

Abstract: A semiconductor packaging substrate with a first major surface and a second major surface with an external connection terminal for electrical connection. One or more first wiring layers are on the first major surface side. The first wiring layer includes a first insulating resin layer and a first conductor circuit layer with includes via hole portions and wiring portions. A seed metal layer is formed on three surfaces to which the first insulating resin layer and the wiring portion are grounded, and one or more second wiring layers are formed on the second major surface side. The second wiring layer includes a second insulating resin layer and a second conductor circuit layer of via hole portions and wiring portions, and a seed metal layer is formed on only one surface in which the wiring portion of the second conductor circuit layer and the second insulating resin layer are grounded.

公开(公告)号：US20190269013A1

公开(公告)日：2019-08-29

申请号：US16404976

申请日：2019-05-07

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Fusao TAKAGI ,  Kiyotomo NAKAMURA

IPC: H05K1/16 ,  H01G4/228 ,  H01G4/33 ,  H01L23/15 ,  H05K3/46 ,  H05K3/38 ,  H01G4/06

Abstract: An electronic component includes a glass base in which through holes are formed passing through both surfaces thereof; an insulating resin layer laminated on each of both surfaces of the glass base and including a copper plated layer formed therein; and a capacitor including a lower electrode formed on the copper plated layer, a dielectric layer laminated on the lower electrode, and an upper electrode laminated on the dielectric layer. In the electronic component, the upper electrode has a region that is parallel to the copper plated layer and is formed so as to be smaller than a region of the dielectric layer parallel to the surface of the copper plated layer or a region of the lower electrode parallel to the surface of the copper plated layer.