公开(公告)号：US07243322B1

公开(公告)日：2007-07-10

申请号：US10859055

申请日：2004-06-01

申请人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Ander ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

发明人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Ander ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5022 ,  G01R31/30

摘要： During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

摘要翻译： 在验证包含预定断言的电路的描述期间，为了检测可能由在电路中交叉时钟域（“CDC”信号）的信号中发生的亚稳态引起的电路的不正确行为，描述 该电路通过添加电路自动转换，以将亚稳态的影响注入到CDC信号中。 以正常方式验证包含注入亚稳态的电路的变换描述。 某些实施例使用模型检查方法分析变换的描述，以确定将导致预定的断言被违反的刺激序列。 在一些实施例中，使用来自模型检查的刺激序列来模拟变换电路，并且显示由于亚稳态引起的电路的错误行为，以供电路设计者进行诊断。 电路设计者可以修改电路描述并如上所述进行迭代。

公开(公告)号：US07454728B2

公开(公告)日：2008-11-18

申请号：US11759888

申请日：2007-06-07

申请人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Andersen ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

发明人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Andersen ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5022 ,  G01R31/30

摘要： During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

摘要翻译： 在验证包含预定断言的电路的描述期间，为了检测可能由在电路中交叉时钟域（“CDC”信号）的信号中发生的亚稳态引起的电路的不正确行为，描述 该电路通过添加电路自动转换，以将亚稳态的影响注入到CDC信号中。 以正常方式验证包含注入亚稳态的电路的变换描述。 某些实施例使用模型检查方法分析变换的描述，以确定将导致预定的断言被违反的刺激序列。 在一些实施例中，使用来自模型检查的刺激序列来模拟变换电路，并且显示由于亚稳态引起的电路的错误行为，以供电路设计者进行诊断。 电路设计者可以修改电路描述并如上所述进行迭代。