公开(公告)号：US20080134115A1

公开(公告)日：2008-06-05

申请号：US12029440

申请日：2008-02-11

申请人： Tai An Ly ,  Ka Kie Kwok ,  Vijaya Vardhan Gupta ,  Lawrence Curtis Widdoes

发明人： Tai An Ly ,  Ka Kie Kwok ,  Vijaya Vardhan Gupta ,  Lawrence Curtis Widdoes

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G01R31/30 ,  G06F17/5022

摘要： A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.

摘要翻译： 包含至少两个时钟域的电路设计使用用于注入亚稳态效应的新型系统和方法进行模拟。 该系统包括检测器，用于在仿真期间当发送时钟域中的时钟和接收时钟域中的时钟对准时以及当接收时钟域交叉信号的寄存器的输入正在改变时进行检测。 该系统包括覆盖监测器，用于在模拟期间测量与亚稳态注入相关的统计。 在仿真期间的适当时间，系统准确地模拟亚稳态的影响，接收时域交叉信号的寄存器的伪随机反转输出。 通过准确地模拟亚稳态的影响，可以在模拟预先存在的模拟测试的同时检测电路设计中的误差。 具有亚稳态效应注入的模拟是可重复的，不需要修改预先存在的RTL设计文件或模拟测试文件。

公开(公告)号：US07712062B2

公开(公告)日：2010-05-04

申请号：US12029440

申请日：2008-02-11

申请人： Tai An Ly ,  Ka Kie Kwok ,  Vijaya Vardhan Gupta ,  Lawrence Curtis Widdoes, Jr.

发明人： Tai An Ly ,  Ka Kie Kwok ,  Vijaya Vardhan Gupta ,  Lawrence Curtis Widdoes, Jr.

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031 ,  G01R31/30 ,  G06F17/5022

摘要： A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.

摘要翻译： 包含至少两个时钟域的电路设计使用用于注入亚稳态效应的新型系统和方法进行模拟。 该系统包括检测器，用于在仿真期间当发送时钟域中的时钟和接收时钟域中的时钟对准时以及当接收时钟域交叉信号的寄存器的输入正在改变时进行检测。 该系统包括覆盖监测器，用于在模拟期间测量与亚稳态注入相关的统计。 在仿真期间的适当时间，系统准确地模拟亚稳态的影响，接收时域交叉信号的寄存器的伪随机反转输出。 通过准确地模拟亚稳态的影响，可以在模拟预先存在的模拟测试的同时检测电路设计中的误差。 具有亚稳态效应注入的模拟是可重复的，不需要修改预先存在的RTL设计文件或模拟测试文件。