公开(公告)号：US20210375672A1

公开(公告)日：2021-12-02

申请号：US17112119

申请日：2020-12-04

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Hao Chun Liu ,  Po-Hao Tsai ,  Chih-Hsien Lin ,  Ching-Wen Hsiao

IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L23/532 ,  H01L23/00

摘要： A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.