公开(公告)号：US12230316B2

公开(公告)日：2025-02-18

申请号：US18412380

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Atuk Katoch

IPC: G11C5/14 ,  G11C11/417 ,  H10B10/00

Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

公开(公告)号：US11900994B2

公开(公告)日：2024-02-13

申请号：US17883998

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Atuk Katoch

IPC: G11C5/14 ,  G11C11/417 ,  H10B10/00

CPC classification number: G11C11/417 ,  G11C5/148 ,  H10B10/12

Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

公开(公告)号：US11488661B2

公开(公告)日：2022-11-01

申请号：US17220701

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Atuk Katoch

IPC: G11C5/14 ,  G11C11/417

Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.