公开(公告)号：US20240379532A1

公开(公告)日：2024-11-14

申请号：US18784638

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-huan WEI ,  Pin Yu HSU ,  Szu-Yuan CHEN ,  Po-June CHEN ,  Kuan-Yu CHEN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process. In one embodiment, a method for fabricating a semiconductor device includes: forming a first conductive feature on a semiconductor substrate; forming a second conductive feature on the semiconductor substrate; forming a first via structure over the first conductive feature; forming a first metallization structure over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure; forming a conductive etch stop structure on the first metallization structure; forming a first via hole above the conductive etch stop structure and a second via hole above the second conductive feature, wherein the first via hole exposes the conductive etch stop structure and the second via hole is deeper than the first via hole; and forming a capacitor in the second via hole.

公开(公告)号：US20200279803A1

公开(公告)日：2020-09-03

申请号：US16856512

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun huan WEI ,  Pin Yu HSU ,  Szu-Yuan CHEN ,  Po-June CHEN ,  Kuan-Yu CHEN

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/532

Abstract: Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process. In one embodiment, a method for fabricating a semiconductor device includes: forming a first conductive feature on a semiconductor substrate; forming a second conductive feature on the semiconductor substrate; forming a first via structure over the first conductive feature; forming a first metallization structure over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure; forming a conductive etch stop structure on the first metallization structure; forming a first via hole above the conductive etch stop structure and a second via hole above the second conductive feature, wherein the first via hole exposes the conductive etch stop structure and the second via hole is deeper than the first via hole; and forming a capacitor in the second via hole.