公开(公告)号：US11256844B2

公开(公告)日：2022-02-22

申请号：US17025296

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yao Ku ,  Wen-Hao Chen ,  Ming-Tao Yu

IPC: G06F30/30 ,  H01L23/528 ,  H01L27/02 ,  G06F30/392 ,  G06F30/398 ,  G06F30/394 ,  G06F111/20 ,  G06F115/06 ,  G06F119/06 ,  G06F119/12

Abstract: A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows.

公开(公告)号：US20190148290A1

公开(公告)日：2019-05-16

申请号：US16023711

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yao KU ,  Wen-Hao CHEN ,  Ming-Tao Yu

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Exemplary embodiments for various via pillar structures include one or more first conductors in a first interconnect layer of a semiconductor stack interconnected with one or more second conductors in a second interconnect layer of the semiconductor stack. The one or more first conductors and/or the one or more second conductors within the first interconnect layer and the second interconnect layer, respectively, can traverse multiple directions. In some situations, this allows multiple interconnections to be utilized to interconnect the one or more first conductors and the one or more second conductors. These multiple interconnections can reduce resistance between the one or more first conductors and the one or more second conductors thereby improving performance of signals flowing between the one or more first conductors and the one or more second conductors.