公开(公告)号：US20190198403A1

公开(公告)日：2019-06-27

申请号：US15855080

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wei FANG ,  Jing-Sen WANG ,  Yuan-Yao CHANG ,  Wei-Ray LIN ,  Ting-Hua HSIEH ,  Pei-Hsuan LEE ,  Yu-Hsuan HUANG

IPC: H01L21/66 ,  G01N21/95 ,  G01N21/88 ,  G01N21/93 ,  G06T7/00

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.