公开(公告)号：US20250031435A1

公开(公告)日：2025-01-23

申请号：US18354954

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Wei Chen ,  Zheng Hui Lim ,  Yen Chuang ,  Shun-Siang Jhan ,  Yi-Ching Hung ,  Ji-Yin Tsai

IPC: H01L21/8238

Abstract: In an embodiment, a method includes: patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, the dummy nanostructure including doped silicon; forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the doped silicon of the dummy nanostructure; forming an isolation structure in the opening; and depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure.