公开(公告)号：US11489681B2

公开(公告)日：2022-11-01

申请号：US17412852

申请日：2021-08-26

Applicant: Taiyuan University of Technology

Inventor： Jianguo Zhang ,  Xin Wang ,  Guodong Zhang ,  Yuncai Wang ,  Pu Li ,  Xianglian Liu

IPC: H04L9/32

Abstract: A physically unclonable function (PUF) device includes a hybrid Boolean network module of a ring of N number of Boolean nodes connected end to end and a sampling module, wherein the hybrid Boolean network module comprises N number of xor logic gates and corresponding N number of multiplexers, wherein a function change module is disposed between an output end of a first xor logic gate of the N number of xor logic gates and an input end of a first multiplexer of the N number of multiplexers, wherein each Boolean node is provided with four input ends and three output ends, the four input ends respectively connected to an output end of each of two juxtaposing Boolean nodes, an initial excitation signal and a control delay signal, the three output ends respectively output to an input of each of two juxtaposing Boolean nodes, and the sampling module.

公开(公告)号：US20220094561A1

公开(公告)日：2022-03-24

申请号：US17412852

申请日：2021-08-26

Applicant: Taiyuan University of Technology

Inventor： Jianguo Zhang ,  Xin Wang ,  Guodong Zhang ,  Yuncai Wang ,  Pu Li ,  Xianglian Liu

IPC: H04L9/32

Abstract: A physically unclonable function (PUF) device includes a hybrid Boolean network module of a ring of N number of Boolean nodes connected end to end and a sampling module, wherein the hybrid Boolean network module comprises N number of xor logic gates and corresponding N number of multiplexers, wherein a function change module is disposed between an output end of a first xor logic gate of the N number of xor logic gates and an input end of a first multiplexer of the N number of multiplexers, wherein each Boolean node is provided with four input ends and three output ends, the four input ends respectively connected to an output end of each of two juxtaposing Boolean nodes, an initial excitation signal and a control delay signal, the three output ends respectively output to an input of each of two juxtaposing Boolean nodes, and the sampling module.