公开(公告)号：US20090293025A1

公开(公告)日：2009-11-26

申请号：US12358888

申请日：2009-01-23

申请人： Takahide Yoshikawa

发明人： Takahide Yoshikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F11/3476 ,  G06F11/348 ,  G06F17/5022 ,  G06F2201/88 ,  G06F2217/78 ,  Y02D10/34

摘要： Designation of observation points in an observation target circuit for which operations are observed in simulation is accepted, and circuit data of an observation circuit is attached to circuit data of the observation target circuit so that the observation circuit is connected to the observation target circuit according to designation data of the observation points. At this time, a double-buffer configuration is adopted for the observation circuit, and the number of occurrence times of a specific state at a specific observation point during a first period and the number of occurrence times of the specific state at the specific observation point during a second period are alternately outputted and stored into RAM.

摘要翻译： 接受在模拟中观察到操作的观察目标电路中的观测点的指定，并且将观测电路的电路数据附加到观察目标电路的电路数据，使得观测电路根据 观察点的指定数据。 此时，观察电路采用双缓冲器配置，在第一时段期间的特定观察点处的特定状态的发生次数和特定观察点处的特定状态的发生次数 在第二时段期间交替输出并存储到RAM中。

公开(公告)号：US20080312881A1

公开(公告)日：2008-12-18

申请号：US12076551

申请日：2008-03-19

申请人： Yuzi Kanazawa ,  Takahide Yoshikawa ,  Tsuneo Nakata

发明人： Yuzi Kanazawa ,  Takahide Yoshikawa ,  Tsuneo Nakata

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.

摘要翻译： 单个模块包括共享组合电路，多路复用顺序电路和公共I / F，并且代替由相同类别和类型的多个模块形成并包括多个CPU的多路复用模块。 具体地，共享组合电路代替n个组合电路，多路复用顺序电路代替n个连续电路，并且公共I / F代替n个输入引脚和n个输出引脚。

公开(公告)号：US08386989B2

公开(公告)日：2013-02-26

申请号：US12358888

申请日：2009-01-23

申请人： Takahide Yoshikawa

发明人： Takahide Yoshikawa

IPC分类号： G06F11/22 ,  G06F17/50

CPC分类号： G06F17/50 ,  G06F11/3476 ,  G06F11/348 ,  G06F17/5022 ,  G06F2201/88 ,  G06F2217/78 ,  Y02D10/34

摘要： Designation of observation points in an observation target circuit for which operations are observed in simulation is accepted, and circuit data of an observation circuit is attached to circuit data of the observation target circuit so that the observation circuit is connected to the observation target circuit according to designation data of the observation points. At this time, a double-buffer configuration is adopted for the observation circuit, and the number of occurrence times of a specific state at a specific observation point during a first period and the number of occurrence times of the specific state at the specific observation point during a second period are alternately outputted and stored into RAM.

摘要翻译： 接受在模拟中观察到操作的观察目标电路中的观测点的指定，并且将观测电路的电路数据附加到观察目标电路的电路数据，使得观测电路根据 观察点的指定数据。 此时，观察电路采用双缓冲器配置，在第一时段期间的特定观察点处的特定状态的发生次数和特定观察点处的特定状态的发生次数 在第二时段期间交替输出并存储到RAM中。

公开(公告)号：US07966590B2

公开(公告)日：2011-06-21

申请号：US12076551

申请日：2008-03-19

申请人： Yuzi Kanazawa ,  Takahide Yoshikawa ,  Tsuneo Nakata

发明人： Yuzi Kanazawa ,  Takahide Yoshikawa ,  Tsuneo Nakata

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.

摘要翻译： 单个模块包括共享组合电路，多路复用顺序电路和公共I / F，并且代替由相同类别和类型的多个模块形成并包括多个CPU的多路复用模块。 具体地，共享组合电路代替n个组合电路，多路复用顺序电路代替n个连续电路，并且公共I / F代替n个输入引脚和n个输出引脚。

公开(公告)号：US20080209368A1

公开(公告)日：2008-08-28

申请号：US12003774

申请日：2007-12-31

申请人： Toshihiko Yokomaru ,  Takahide Yoshikawa

发明人： Toshihiko Yokomaru ,  Takahide Yoshikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An apparatus for designing the layout of a circuit includes an acquiring unit, a determining unit, a specifying unit, an arranging unit, a modifying unit, and a routing unit. Based on net information acquired by the acquiring unit, the determining unit determines a wiring block of signal paths connecting cells connected through adjacent. The arranging unit arranges a wiring area between the cells that extends along user-specified reference points or user-specified reference segments received by the specifying unit. The modifying unit modifies the arranged wiring area and the routing unit routes the signal paths of the wiring block in the modified wiring area.

摘要翻译： 一种用于设计电路布局的装置包括获取单元，确定单元，指定单元，布置单元，修改单元和布线单元。 基于由获取单元获取的净信息，确定单元确定连接通过相邻单元连接的单元的信号路径的布线块。 布置单元沿着沿着指定单元接收的用户指定的参考点或用户指定的参考段延伸的单元之间布置布线区域。 修改单元修改布置的布线区域，并且路由单元路由修改的布线区域中的布线块的信号路径。