公开(公告)号：US08116119B1

公开(公告)日：2012-02-14

申请号：US12758579

申请日：2010-04-12

申请人： Tao Peng ,  Hsiao Hui Chen

发明人： Tao Peng ,  Hsiao Hui Chen

IPC分类号： G11C11/00

CPC分类号： G11C7/08 ,  G11C7/14 ,  G11C8/16 ,  G11C11/413 ,  Y10S257/903

摘要： A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array is turned off responsive to the signal. The write replica circuit can include an additional column comprising at least one dual port dummy memory cell, and write detection circuitry coupled to the dual port dummy memory cell detecting when data has been written to the dual port dummy memory cell and responsively generating the signal. The signal generated by the write detection circuitry indicates a successful write operation to the dual port dummy memory cell.

摘要翻译： 静态随机存取存储器（SRAM）可以包括形成存储器阵列的多个列，其中每列包括耦合到位线和字线的多个存储单元，以及当数据被写入写入时产生信号的写复制电路 复制电路。 根据信号，存储器阵列的字线被关闭。 写复制电路可以包括包括至少一个双端口虚拟存储器单元的附加列，以及耦合到双端口虚拟存储器单元的写入检测电路，当数据被写入双端口虚拟存储器单元并且响应地生成信号时，该检测电路被检测。 由写检测电路产生的信号指示对双端口伪存储器单元的成功写操作。

公开(公告)号：US07746717B1

公开(公告)日：2010-06-29

申请号：US11899825

申请日：2007-09-07

申请人： Tao Peng ,  Hsiao Hui Chen

发明人： Tao Peng ,  Hsiao Hui Chen

IPC分类号： G11C7/02

CPC分类号： G11C7/08 ,  G11C7/14 ,  G11C8/16 ,  G11C11/413 ,  Y10S257/903

摘要： A static random access memory (SRAM) can include an array of memory cells, wherein each memory cell is coupled to one of a plurality of sense amplifiers through a bitline. The SRAM also can include replica bitline circuitry including a replica bitline coupled to a replica bitline amplifier. The replica bitline amplifier can provide a strobe signal to the plurality of sense amplifiers, wherein the replica bitline amplifier includes a feedback path. An SRAM also may include a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array can be turned off responsive to the signal.

摘要翻译： 静态随机存取存储器（SRAM）可以包括存储器单元的阵列，其中每个存储器单元通过位线耦合到多个读出放大器之一。 SRAM还可以包括复制位线电路，包括耦合到复制位线放大器的复制位线。 复制位线放大器可以向多个读出放大器提供选通信号，其中复制位线放大器包括反馈路径。 当数据已被写入到写入复制电路时，SRAM还可以包括写复制电路，产生信号。 存储器阵列的字线可以响应于该信号而被关闭。