公开(公告)号：US20220284293A1

公开(公告)日：2022-09-08

申请号：US17447625

申请日：2021-09-14

Applicant: Tata Consultancy Services Limited

Inventor： Swarnava DEY ,  Arpan PAL ,  Gitesh KULKARNI ,  Chirabrata BHAUMIK ,  Arijit UKIL ,  Jayeeta MONDAL ,  Ishan SAHU ,  Aakash TYAGI ,  Amit SWAIN ,  Arijit MUKHERJEE

IPC: G06N3/08 ,  G06N3/063 ,  G06F1/3206 ,  G06K9/62

Abstract: Small and compact Deep Learning models are required for embedded Al in several domains. In many industrial use-cases, there are requirements to transform already trained models to ensemble embedded systems or re-train those for a given deployment scenario, with limited data for transfer learning. Moreover, the hardware platforms used in embedded application include FPGAs, AI hardware accelerators, System-on-Chips and on-premises computing elements (Fog/Network Edge). These are interconnected through heterogenous bus/network with different capacities. Method of the present disclosure finds how to automatically partition a given DNN into ensemble devices, considering the effect of accuracy—latency power—tradeoff, due to intermediate compression and effect of quantization due to conversion to AI accelerator SDKs. Method of the present disclosure is an iterative approach to obtain a set of partitions by repeatedly refining the partitions and generating a cascaded model for inference and training on ensemble hardware.