公开(公告)号：US20080106301A1

公开(公告)日：2008-05-08

申请号：US11924627

申请日：2007-10-26

申请人： Tetsuo FUKUSHI

发明人： Tetsuo FUKUSHI

IPC分类号： H03K19/0175

CPC分类号： H03K19/0005

摘要： A semiconductor integrated circuit includes an output driver, a replica driver, a replica resistor, and an impedance adjustment circuit. The output driver is configured to be capable of changing current driving capability. The replica driver is configured to be capable of changing current driving capability. The replica resistor is connected to an output of the replica driver. The impedance adjustment circuit is configured to adjust the current driving capability of the output driver and the replica driver, based on an output voltage of the replica driver. In addition, the output driver, the replica driver, the replica resistor, and the impedance adjustment circuit are mounted in an integrated circuit package.

摘要翻译： 半导体集成电路包括输出驱动器，复制驱动器，复制电阻器和阻抗调整电路。 输出驱动器被配置为能够改变电流驱动能力。 复制驱动器被配置为能够改变当前驱动能力。 复制电阻连接到副本驱动器的输出。 阻抗调整电路被配置为基于副本驱动器的输出电压来调节输出驱动器和副本驱动器的电流驱动能力。 此外，输出驱动器，复制驱动器，复制电阻器和阻抗调节电路安装在集成电路封装中。

公开(公告)号：US20120250445A1

公开(公告)日：2012-10-04

申请号：US13432967

申请日：2012-03-28

申请人： Yasuharu HOSHINO ,  Toshihiko FUNAKI ,  Atsunori HIROBE ,  Tetsuo FUKUSHI

发明人： Yasuharu HOSHINO ,  Toshihiko FUNAKI ,  Atsunori HIROBE ,  Tetsuo FUKUSHI

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C7/10 ,  G11C7/109 ,  H03K19/17752

摘要： A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal.

摘要翻译： 半导体装置包括被配置为输出控制信号的可编程逻辑芯片和耦合到可编程逻辑芯片的存储器芯片。 存储器芯片包括多个存储器核，多个总线接口电路，每个被配置为与存储器核心耦合;以及选择电路，被配置为响应于预定逻辑将存储器核与总线接口电路之一耦合 控制信号的电平。