公开(公告)号：US07178008B2

公开(公告)日：2007-02-13

申请号：US10370172

申请日：2003-02-18

申请人： Tetsuo Hironaka ,  Mattausch Hans Juergen ,  Takeshi Hiramatsu

发明人： Tetsuo Hironaka ,  Mattausch Hans Juergen ,  Takeshi Hiramatsu

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3012 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3885

摘要： A parallel processor has a plurality of operation units that execute operation instructions, and a multi-bank register file in which a plurality of banks each having a plurality of registers are formed. Each of machine instructions, which are input simultaneously, is split into a plurality of nano-instructions each of which includes at least one of an access instruction and operation instruction. The output clock cycles of operation instructions with respect to the operation units are arbitrated. Furthermore, the output clock cycles of access instructions to the multi-bank register file are arbitrated so as to prevent access instructions from contending in an identical bank in the multi-bank register file.

摘要翻译： 并行处理器具有执行操作指令的多个操作单元，以及多存储体寄存器堆，其中形成多个具有多个寄存器的存储体。 每个同时输入的机器指令被分割成多个纳入指令，每个指令包括访问指令和操作指令中的至少一个。 对操作单元的操作指令的输出时钟周期进行仲裁。 此外，对多存储体寄存器堆的访问指令的输出时钟周期进行仲裁，以防止访问指令在多存储体寄存器堆中的相同存储体中竞争。