公开(公告)号：US20250111007A1

公开(公告)日：2025-04-03

申请号：US18901256

申请日：2024-09-30

Applicant: Texas Instruments Incorporated

Inventor： Kanish B ,  Karthik Subburaj ,  Karthik Ramasubramanian ,  Anushree Pendharkar ,  Kameswaran Vengattaramane ,  Atman Kar

IPC: G06F17/14 ,  G06F7/50 ,  G06F7/523

Abstract: In described examples, an integrated circuit (IC) includes a fast Fourier transform (FFT) engine, a first memory, a second memory, a conjugate symmetric combiner (CSC), and a control circuit coupled to control them. The first and second memories are coupled to the FFT engine, and the CSC is coupled to the first and second memories and the FFT engine. The FFT engine receives and processes a first stream of samples to generate a second stream of samples. In a first phase, the FFT engine provides a first portion of the second stream of samples to the first memory. In a second phase, the FFT engine provides a second portion of the second stream of samples to the second memory, the first memory provides the first portion of the second stream of samples to the CSC, and the CSC responsively generates a third stream of samples.